Safety-critical platooning function based on wireless communication using cooperative robots

Platooning define la conducción de un grupo de vehículos con un destino o dirección común, en la que el primer vehículo decide sobre la conducción (p. ej. aceleración, cambio de carril, desvío, etc.) y los demás se restringen a seguirlo. Estos vehículos pueden ser conducidos por un ser humano o de forma automática. Además, los vehículos comparten información entre sí permitiendo mantener una distancia de seguridad mínima entre ellos, lo que reduce el consumo de combustible y compacta el tráfico en las carreteras sin incrementar el riesgo de colisiones. Esta tesis propone una serie de escenarios basados en platooning y define un plano de control distribuido entre los vehículos que integra un protocolo de comunicación y un protocolo de control necesarios para conseguir realizar los escenarios de platooning, propuestos. Tanto los escenarios como la pila de protocolos para la comunicación que se han propuesto están basados en trabajo previo descrito en artículos de investigación. Estos artículos explican y prueban estándares y tecnologías adecuadas para desarrollar las funcionalidades de platooning definidas en la tesis. La principal tarea en esta tesis es el diseño de un protocolo de comunicación en alto nivel, capa de aplicación del modelo OSI, el cual define un conjunto de mensajes que al combinarlos permiten implementar una serie de funciones de platooning, en concreto permiten la implementación de los escenarios descritos en la tesis. Además de diseñar este protocolo de comunicación, se han implementado y probado en una plataforma real sencillas funciones de platooning. En la tesis también se analiza el protocolo, se buscan soluciones para soportar fallos de comunicación en la implementación y se evalúa la actuación de la implementación en base a unas métricas previamente definidas. Los test realizados sobre la implementación y los resultados obtenidos en la evaluación muestran que el protocolo diseñado permite ejecutar correctamente los escenarios de platooning deseados

Lightweight protection of cryptographic hardware accelerators against differential fault analysis

© 2020 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes,creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.Hardware acceleration circuits for cryptographic algorithms are largely deployed in a wide range of products. The HW implementations of such algorithms often suffer from a number of vulnerabilities that expose systems to several attacks, e.g., differential fault analysis (DFA). The challenge for designers is to protect cryptographic accelerators in a cost-effective and power-efficient way. In this paper, we propose a lightweight technique for protecting hardware accelerators implementing AES and SHA-2 (which are two widely used NIST standards) against DFA. The proposed technique exploits partial redundancy to first detect the occurrence of a fault and then to react to the attack by obfuscating the output values. An experimental campaign demonstrated that the overhead introduced is 8.32% for AES and 3.88% for SHA-2 in terms of area, 0.81% for AES and 12.31% for SHA-2 in terms of power with no working frequency reduction. Moreover, a comparative analysis showed that our proposal outperforms the most recent related countermeasures.Peer ReviewedPostprint (author's final draft

Detection of hardware trojans and DFA attacks on cryptographic systems through residue checking

Residue checking technique can detect security attacks on cryptographic accelerators. This mechanism is tested using an RTL language on AES, RSA and SHA-1 algorithms. The implementation detects hardware Trojans modifying the value of the signals in the system and DFA attacks

Detection of hardware trojans and DFA attacks on cryptographic systems through residue checking

Residue checking technique can detect security attacks on cryptographic accelerators. This mechanism is tested using an RTL language on AES, RSA and SHA-1 algorithms. The implementation detects hardware Trojans modifying the value of the signals in the system and DFA attacks

Detection of hardware trojans and DFA attacks on cryptographic systems through residue checking

Residue checking technique can detect security attacks on cryptographic accelerators. This mechanism is tested using an RTL language on AES, RSA and SHA-1 algorithms. The implementation detects hardware Trojans modifying the value of the signals in the system and DFA attacks

Securing RSA hardware accelerators through residue checking

none4noneLasheras, Ana; Canal, Ramon; Rodríguez, Eva; Cassano, LucaLasheras, Ana; Canal, Ramon; Rodríguez, Eva; Cassano, Luc

Protecting RSA hardware accelerators against differential fault analysis through residue checking

© 2019 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes,creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.Hardware accelerators for cryptographic algorithms are ubiquitously deployed in nowadays consumer and industrial products. Unfortunately, the HW implementations of such algorithms often suffer from vulnerabilities that expose systems to a number of attacks, among which differential fault analysis (DFA). It is therefore crucial to protect cryptographic circuits against such attacks in a cost-effective and power-efficient way. In this paper, we propose a lightweight technique for protecting circuits implementing the RSA algorithm against DFA. The proposed solution borrows residue checking from the traditional fault tolerance and applies it to RSA circuits in order to first detect the occurrence a fault and then to react to the attack by obfuscating the output values. An experimental campaign demonstrated that the proposed solution detects the 100% of the possible fault attacks while leading to a 2.85% area overhead, a 16.67% power consumption increase and with no operating frequency decrease.Peer Reviewe